The present invention relates to a delay locked loop circuit, and more particularly, to a delay locked loop circuit having improved external noise characteristics.
In general, a delay locked loop DLL is a circuit that controls a timing of outputting data from a synchronous memory device using an external clock inputted from the outside of the synchronous memory device.
In order to transmit data from the semiconductor memory device to a chipset without an error, the semiconductor memory device and the chipset are synchronized with the external clock. However, the external clock inputted to the semiconductor memory device is delayed by an internal circuit of the semiconductor memory device. Therefore, a phase difference between the external clock and the internal clock occurs. The DLL removes a phase difference between a clock and data output from the semiconductor memory device by compensating a clock skew generated in the internal circuit of the semiconductor memory device.
FIG. 1 is a block diagram illustrating a delay locked loop according to the related art.
As shown, the delay locked loop according to the related art includes a phase comparator 101, a delay controller 103, a delay unit 105, and a replica model unit 107.
The phase comparator 101 compares a phase of an external clock EXT_CLK with a phase of a feedback clock FB_CLK output from the replica model unit 107, which is generated by modeling a clock delay component inside a semiconductor memory device, and outputs a phase comparison signal CMP that denotes a phase difference between the external clock EXT_CLK and the feedback clock FB_CLK. The delay controller 103 determines a delay amount of an internal clock in response to the phase comparison signal CMP and outputs a delay control signal DELAY to the delay unit 105. The delay unit 105 delays the external clock EXT_CLK as much as a first delay amount DD_1 (see FIG. 2) in response to the delay control signal DELAY and outputs the delayed external clock as an internal clock CLK_OUTFIG. The internal clock CLK_OUT is inputted to the replica model unit 107, which, for example, replicates physical properties of a semiconductor device with respect to signal delays.
Finally, a phase of the feedback clock from the replica model unit 107 is synchronized with a phase of the external clock EXT_CLK by reflecting the delay of the delay unit 105 and the replica model unit, which replicates physical properties of a semiconductor device with respect to signal delays. Here, the internal clock CLK_OUT delayed from the delay unit 105 is locked.
Meanwhile, delay may be caused by elements of the delay locked loop circuit due to a power noise (for example, a supply voltage may be abruptly reduced). When a supply voltage, that drives a delay looked loop circuit, is drastically reduced, the elements of the delay locked loop circuit cannot be driven normally with this supply voltage. On the other hand, if the supply voltage for driving the delay locked loop increases, a signal inputted to the elements of the delay locked loop circuit may be outputted with a reduced delay amount.
If the external noise is continuously inputted to the delay locked loop circuit, the external clock EXT_CLK is delayed only when the external noise is inputted. However, unlike the delay amount of the external clock EXT_CLK, the delay amount of the feedback clock FB_CLK is accumulated because the feedback clock FB_CLK is generated with delay reflected by the delay unit 105 and the replica model unit 107 which are influenced by the external noise. Finally, the feedback clock FB_CLK is delayed as much as a third delay amount DD_3 (see FIG. 2), which is an amount of delay caused by the continuously inputted external noise, and inputted to the phase comparator 101. Therefore, the phase comparator 101 reflects the delay amount of the feedback clock FB_CLK caused by the external noise and outputs the phase comparison signal CMP. Finally, the internal clock CLK_OUT is locked with the unintended delay amount caused by the external noise.
FIG. 2 is a timing diagram illustrating operation of a delay locked loop circuit of FIG. 1. FIG. 2 shows the influence of power noise on a locking process of an internal clock CLK_OUT.
When the delay locked loop circuit operates initially, the external clock EXT_CLK is not delayed by the delay unit 105 because the delay amount of the delay unit 105 is under a reset state. Therefore, a phase of the external clock EXT_CLK is not synchronized with a phase of the internal clock CLK_OUT. A phase of the feedback clock FB_CLK output from the replica model unit 107 is different from a phase of the external clock EXT_CLK by as much as a first delay amount DD_1 of the replica model unit 107 since there is no delay through the delay unit 105 initially. The phase comparator 101 detects the phase difference between the feedback clock FB_CLK and the external clock EXT_CLK and outputs the phase comparison signal CMP to the delay controller 103. The delay controller 103 determines the delay amount of the internal clock CLK_OUT in response to the phase comparison signal CMP, and the delay unit 105 delays the external clock EXT_CLK as much as the first delay amount DD_1 and outputs a delayed external clock as the internal clock CLK_OUT.
Since the feedback clock FB_CLK is generated in response to the internal clock CLK_OUT inputted to the replica model 107, a phase of the external clock EXT_CLK is synchronized with a phase of the feedback clock FB_CLK. Here, the internal clock is locked. A phase difference between the internal clock CLK_OUT and the external clock EXT_CLK is a first phase difference DD_1 which is a phase difference of the internal clock CLK_OUT and the feedback clock FB_CLK and corresponds to a delay through the replica model 107.
If external noise is continuously inputted to the delay locked loop circuit after locking, the feedback clock FB_CLK may be delayed as much as a third delay amount DD_3 as shown. Therefore, the phase comparator 101 detects the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK and outputs the phase comparison signal CMP. The delay controller 103 outputs the delay control signal DELAY for reducing the delay amount of the internal clock CLK_OUT to the delay unit 105 in response to the phase comparison signal CMP. The delay unit 105 outputs the internal clock CLK_OUT of which the delay amount is reduced as much as the third delay amount DD_3. Finally, the internal clock CLK_OUT is locked with a smaller delay amount than the first delay amount DD1 to compensate for the external noise.
If the external noise disappears, the delay amount of the feedback clock FB_CLK is reduced as much as the third delay amount DD_3, and the internal clock CLK_OUT may be locked as the first delay amount DD_1 again by the locking process.
Finally, if an external noise such as a power source noise is inputted, the internal clock CLK_OUT is locked with an unintended delay amount. Until the internal clock CLK_OUT is locked after the external noise disappears, the skew of the external clock EXT_CLK and the internal clock CLK_OUT is caused by the external noise when the semiconductor memory device outputs data, and the data output from the semiconductor memory device may have an error.